c - cc command does not work to create object file

Question

I'm trying to create a makefile that runs a basic Hello World file seen here:

#include <stdio.h>

int main() {
    printf("Hello World");
    return 0;
}

And my makefile:

CFLAGS = -Wall -g

helloworld: helloworld.o
    cc -o helloworld helloworld.o

clean:
    rm helloworld helloworld.o

I keep getting an error that fails to run cc -Wall -g -c -o helloworld.o helloworld.c. I looked at another stack overflow that says that cc may not be installed? But I understand that cc is just the c compiler but I usually use gcc(which cc is an alias of) to compile the file without makefile but even when I use gcc in the makefile I still get an error. Here is the entire error:

C:est>make -f makefile.mk
cc -Wall -g   -c -o helloworld.o helloworld.c
process_begin: CreateProcess(NULL, cc -Wall -g -c -o helloworld.o helloworld.c, ...) failed.
make (e=2): The system cannot find the file specified.
make: *** [helloworld1.o] Error 2

Any help would be great.

question from:https://stackoverflow.com/questions/65545419/cc-command-does-not-work-to-create-object-file

Answer 1

You are using a built-in rule that make provides for you, to compile a C source file into an object file. You can tell this, because you didn't write any rule telling make how to compile an object file (you have a rule telling make how to link an already-built object file into an executable), so you know that, since make found a rule, it's using one of its built-in rules.

The built-in rules use built-in variables to control them. The list of built-in variables is described in the GNU make manual.

If you examine the list of built-in variables, you'll see that the name of the C compiler is controlled by the CC variable in GNU make (please keep in mind that makefiles, like virtually all POSIX-based tools, which make definitely is, ARE case-sensitive!! The variable cc is just as surely a different variable from CC as the variable foo is from bar).

So, add this to your makefile and hopefully it will work:

CC = gcc

Write your makefile like this:

CC = gcc
CFLAGS = -Wall -g

helloworld: helloworld.o
        $(CC) -o helloworld helloworld.o

clean:
        rm helloworld helloworld.o