vhdl - For loop equivalent RTL description

Question

Coming from a software background, it is still hard for me to think hardware. What would be the equivalent of a for loop in RTL language (VHDL or Verilog) ? I guess I need one register to build a counter, and a multiplexer for branching, is it ?

Answer 1

A VHDL process or Verilog always block is a little bit of software that models a little bit of hardware. A process has a sensitivity list: this is the list of inputs. Should any of these change, then process (ie the little bit of software) executes and the output(s) of the process (any signal driven by that process) get(s) assigned.

For combinational logic, any input always results in the same output, hence you can write a truth table. Your little bit of software is describing the truth table. You could do this using a case statement but that would be impractical for a large number of inputs. Instead, we use some other software-style constructs, such as if statements, loops, arithmetic operators and so on. The purpose of a logic synthesiser is to design a little bit of hardware that behaves in exactly the same way as your little bit of software. In doing this, the logic synthesiser could evaluate your little bit of sofware to determine it's truth table and then could design its little bit of hardware based on that. However, a real logic synthesiser will use a variety of techniques to achieve the same thing.

So, if you put a for loop in your process, if your little bit of software includes a loop, then you will just get a block combinational logic. The for loop will determine the behaviour of that block. Because of the nature of a for loop (and because of the way in which your logic synthesiser probably goes about designing its little bit of hardware), that combination logic will probably contain repeated structures. That may be important when you consider how that block will be implemented, particularly on an FPGA. It may be important with regards to the delay through the block. However, the most important thing is that it will be a block of combinational logic.