verilog always empty sensitivity list

Question

always clk <= #5 !clk;

Seems this doesn`t work and get a "out-of-memory" errors with VCS

What's the reason behind this? I have the feeling the VCS can't get out of the event it scheduled for clk. but don't know why?

Answer 1

You are getting an "out-of-memory" error because it is an non-blocking infinite loop adding future events to the scheduler.

always is functionally equivalent to initial while(1) (an infinite loop). <= #5 doesn't consume time, it schedules an update in the future. There is no time blocking delays in the loop.

Without a time blocking delay the simulator keeps executing the same loop in the same time step. The simulate will not move to the next time step until all operations in the current time step are complete or suspended. Eventually the simulator will run out of memory and error out. Some simulators may exit out early if an infinite loop is detected.

Typically, clocks are generated with LHS delays and with blocking statements. Examples:

reg clk = 1'b1; // or 1'b0
always #5 clk = !clk;

or

reg clk;
initial begin
  clk = 1'b1; // or 1'b0
  forever #5 clk = !clk;
end