digital logic - Verilog Subtraction and addition

Question

I am attempting to program an addition and subtraction program in Verilog. Problem is Implementation and testing in Verilog of a module that performs Addition or Subtraction, then a Mux chooses between letting go through the result of one or the other, and then Decode the selected result from binary into a 7-segment Display format. Verilog Module will have 3 inputs: two 4-bit inputs named A and B, and a select input S. Your circuit should add the two numbers and should also subtract B from A (it is as simple as having A-B in your code). Depending on the value of S (i.e. whether it’s a one or a zero), you should let either the result of the addition or the result of the subtraction through.

This is the code that I have: module AddOrSubtractThenSelectAndDecodeInto7SegmentsDisplay(A,B,S,Result,Overflow,Display);

input [3:0] A;
input [3:0] B;
input [1:0] S;

output reg [3:0] Result;
output reg Overflow;
output reg [6:0] Display;

wire [3:0] A;
wire [3:0] B;
wire [1:0] S;



always @(A,B) begin
    if (S == 0'b0)
        {Overflow, Result} = A - B;
    else if (S == 1'b1)
        {Overflow, Result} = A + B;
    end

always @(Overflow,Result) begin
    case (Result)
        4'b0000: Display = 7'b1111110;//0
        4'b0001: Display = 7'b0110000;//1
        4'b0010: Display = 7'b1101101;//2
        4'b0011: Display = 7'b1111001;//3
        4'b0100: Display = 7'b0110011;//4
        4'b0101: Display = 7'b1011011;//5
        4'b0110: Display = 7'b1011111;//6
        4'b0111: Display = 7'b1110000;//7
        4'b1000: Display = 7'b1111111;//8
        4'b1001: Display = 7'b1111011;//9
        4'b1010: Display = 7'b1110111;//A
        4'b1011: Display = 7'b0011111;//B
        4'b1100: Display = 7'b1001110;//C
        4'b1101: Display = 7'b0111101;//D
        4'b1110: Display = 7'b1001111;//E
        4'b1111: Display = 7'b1000111;//F
        default: Display = 7'bx;
    endcase

    if (Overflow == 1)begin
        Result = 4'bx;
        Display = 7'b0011101;
    end
end


endmodule

When I run the instructors test bench all the lines are green except for display. It says Display[6:0] xxxxxxx and followed by red lines. I have spent 2 days looking at this trying to fix it. Any help please?

Answer 1

The issue with your code, is that you have done assignment on the same net, through more than 1 always block.

Do not make assignments to the same variable from more than one always block.

So your code should be like this :

input [3:0] A;
input [3:0] B;
input [1:0] S;

output [3:0] Result;
output reg Overflow;
output reg [6:0] Display;

reg [3:0] Result_reg;

wire [3:0] A;
wire [3:0] B;
wire [1:0] S;

assign Result = (Overflow) ? 4'bx : Result_reg;

always @(A,B) begin
    if (S == 0'b0)
        {Overflow, Result_reg} = A - B;
    else if (S == 1'b1)
        {Overflow, Result_reg} = A + B;
    end

always @(Overflow,Result_reg) begin
    case ({Overflow, Result_reg}) inside
        [5'b1000:5'b11111] : Display = 7'b0011101; 
        5'b00000: Display = 7'b1111110;//0
        5'b00001: Display = 7'b0110000;//1
        5'b00010: Display = 7'b1101101;//2
        5'b00011: Display = 7'b1111001;//3
        5'b00100: Display = 7'b0110011;//4
        5'b00101: Display = 7'b1011011;//5
        5'b00110: Display = 7'b1011111;//6
        5'b00111: Display = 7'b1110000;//7
        5'b01000: Display = 7'b1111111;//8
        5'b01001: Display = 7'b1111011;//9
        5'b01010: Display = 7'b1110111;//A
        5'b01011: Display = 7'b0011111;//B
        5'b01100: Display = 7'b1001110;//C
        5'b01101: Display = 7'b0111101;//D
        5'b01110: Display = 7'b1001111;//E
        5'b01111: Display = 7'b1000111;//F
        default: Display = 7'bx;
    endcase
end

For Verilog Coding Guidelines, you can check Verilog Coding Guidelines

Moreover, I have assigned "x" in the code, as per your original code. But I am strongly not recommending usage of "x" assignment for RTL code.