Trying to use a buffer in VHDL - not working

Question

My code produces the following error when compiling:

ERROR:HDLCompiler:439 - "E:/ELECTRONIC ENGINEERING 2/DIGITAL/Resit_Year/Assignment_7_seg/4_Bit_Counter/Bit_Counter/counter_tb.vhd" Line 47: Formal port count_out of mode buffer cannot be associated with actual port count_out of mode out ERROR:Simulator:777 - Static elaboration of top level VHDL design unit counter_tb in library work failed

don't know how to fix this.

full code:

-----------------------------------------------------------------------------------
    entity Four_Bit_Counter is

    Port ( clock : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           pause : in  STD_LOGIC;
           count_out : buffer  STD_LOGIC_VECTOR (3 downto 0);
              student_id : buffer STD_LOGIC_VECTOR (3 downto 0)  ); 
      end Four_Bit_Counter;

----------------------------------------------------------------------------------
     architecture Behavioral of Four_Bit_Counter is

    signal temp_count : std_logic_vector(3 downto 0) := "0000" ;
    signal slow_clock : std_logic ;
    signal clock_divider : std_logic_vector(1 downto 0) := "00";
     variable cout_out : std_logic_vector(3 downto 0):= "0000";


    begin

---------------------------------------------------------------------------------

    clock_division : process (clock, clock_divider)

    begin

    if 
        clock'event and clock = '1' then
       clock_divider <= clock_divider + 1;

    end if;

    slow_clock <= clock_divider(1);

     end process;

--------------------------------------------------------------------------------
      counting : process(reset, pause, slow_clock, temp_count)

     begin

     if     reset = '1' then
            temp_count <= "0000";

        elsif pause = '1' then
            temp_count <= temp_count;
    else
    if slow_clock'event and slow_clock= '1' then
    if temp_count < 15 then
    temp_count <= temp_count + 1;
        else
            temp_count <= "0000";
            end if;
        end if;
    end if;

    count_out <= temp_count;

    end process;

----------------------------------------------------------------------------------
student : process (reset, pause, slow_clock, temp_count)

begin


            IF (cout_out = "0010")  THEN
            student_id <= "0010";
            ELSIF (cout_out = "0011")  THEN
            student_id <= "0001";
            ELSIF (cout_out = "0100")  THEN
            student_id <= "0000";
            ELSIF (cout_out = "0101")  THEN
            student_id <= "0000";
            ELSIF (cout_out = "0110")  THEN
            student_id <= "1001";
            ELSIF (cout_out = "0111")  THEN
            student_id <= "0011";
            ELSIF (cout_out = "1000")  THEN
            student_id <= "0010";
            ELSIF (cout_out = "1001")  THEN
            student_id <= "0110";
            ELSE student_id <= "1000";

            END IF;

end process student;

    --student_id <=  "0010" when count_out >= "0001" else
                        --"0001" when count_out >= "0011" else
                        --"0000" when count_out >= "0101" else
                        --"0000" when count_out >= "0111" else
                        --"1001" when count_out >= "1000" else
                        --"0011" when count_out >= "1001" else
                        --"0000" when count_out >= "1011" else
                        --"0110" when count_out >= "1100" else
                        --"1000";



end Behavioral;

Answer 1

Old style VHDL : Buffer ports must be connected to Buffer ports (not Out ports) all the way up the hierarchy. The reason behind this made sense in the early days of VHDL but ASIC and FPGA technology has moved on, so has synthesis technology.

Old style solution : So make the out port in entity (you haven't posted enough code so I can't name it, but it's the next level up in the hierarchy) a buffer port too.

Workaround : If you're not allowed to change the port type in the higher level, you can connect the Buffer port to a signal, and assign that signal to the out port.

Newer VHDL : in VHDL-2002 this restriction was eliminated, so this should work if you select --std=vhdl2002 or equivalent option when compiling.

Newest VHDL : Because Buffer has been so poorly taught it's created so much confusion, that if you select --std=vhdl2008, out ports now allow reading the driving value just like buffer ports, so you can simply replace your buffer ports with out ports.