Recent questions tagged vhdl

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - shift a std_logic_vector of n bit to right or left

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1.5k views 1 answer

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - Using std_logic_vector with logical operators

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547 views 1 answer

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - How to access implicit "=" function for an array type when it is overloaded in the same package?

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464 views 1 answer

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - clk'event vs rising_edge()

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650 views 1 answer

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - clk'event vs rising_edge()

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904 views 1 answer

asked Oct 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - Reset of FIFO (Asynchronous or Synchronous) obtained during instantiating FIFO from IP core of XILINX ISE is active low or active high?

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566 views 1 answer

asked Oct 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - Error: Signal parameter requires signal expression on function call

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612 views 1 answer

asked Oct 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - "GT0 is not compiled in xil_defaultlib" and "gt is not declared"

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1.1k views 1 answer

asked Mar 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - 读/写具有时钟上升沿和读/写使能信号的向量数组(Read/writing to array of vectors with clock rising edge and read/write enable signal)

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574 views 1 answer

asked Mar 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - 读/写具有时钟上升沿和读/写使能信号的向量数组(Read/writing to array of vectors with clock rising edge and read/write enable signal)

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578 views 1 answer

asked Mar 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - 读/写具有时钟上升沿和读/写使能信号的向量数组(Read/writing to array of vectors with clock rising edge and read/write enable signal)

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541 views 1 answer

asked Feb 21, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - 读/写具有时钟上升沿和读/写使能信号的向量数组(Read/writing to array of vectors with clock rising edge and read/write enable signal)

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555 views 1 answer

asked Feb 21, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - 读/写具有时钟上升沿和读/写使能信号的向量数组(Read/writing to array of vectors with clock rising edge and read/write enable signal)

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591 views 1 answer

asked Feb 19, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - waveform does not work properly for some operations

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567 views 1 answer

asked Feb 19, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - Intel Quartus Error 12002 Port does not exist in macrofunction

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965 views 1 answer

asked Feb 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

vhdl - An issue regarding multiple drivers on a wire, error: [DRC MDRV-1] Multiple Driver Nets: Net led_OBUF[0] has multiple drivers: led_OBUF[0]_inst_i_1/O

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795 views 1 answer

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