I am eager to know if there is any real world application which includes following scenario:
Megabytes of continuous write-only to DRAM simultaneously from all (three or more) A53 cores (or any other Arm cores) – throughout the application as the only operation from the core.
The reason why I am asking is, I came accross a specific scenario while designing a chip in which the above operation is misbehaving, so would like to explore how to handle this specific scenario if it's valid.
I could think of only DRAM initialisation.
question from:https://stackoverflow.com/questions/65890792/real-world-dram-write-only-application
